The present invention relates generally to integrated circuits, and, more particularly, to a power management controller (PMC) for an integrated circuit (IC).
Integrated circuits include various analog and digital circuits such as operational amplifiers, sensors, logic circuits, and registers. With advancements in semiconductor technology, the number of circuits has increased dramatically. The increase in the number of circuits on a chip has increased power consumption, resulting in an increase in the heat generated by the IC, which can adversely affect the performance of the IC. To reduce power consumption, certain circuitry is placed in separate domains and these domains are separately powered with different voltage supplies (i.e., voltage supplies with different voltage levels). Thus, ICs include multiple voltage domains that can be switched ON and OFF based on operational requirements.
Such an IC also may be configured to operate in various operational modes, such as functional mode, sleep mode, deep sleep mode, etc., while the voltage domains may include high, low, and ultra-low power voltage domains. A high power voltage domain operates at a high voltage level, i.e., receives a voltage supply at a high voltage level and an ultra-low power voltage domain operates at a low voltage level. For example, the high voltage level may be 1.2 volts (V) and the low voltage level may be 1.125V. When the IC is powered up, the voltage domains are reset to a predetermined state based on predetermined values stored in registers of the voltage domains.
The IC includes a PMC for supplying voltage signals to the voltage domains. The PMC includes multiple voltage regulators for providing multiple voltage signals at various voltage levels. For example, the PMC may include a high power voltage regulator (HPREG) for providing a high voltage signal to the high power voltage domain, a low power voltage regulator (LPREG) for providing a low voltage signal to the low power voltage domain, and an ultra-low power voltage regulator (ULPREG) for providing an ultra-low power voltage signal to the ultra-low power voltage domain. Further, the PMC generates domain reset signals for resetting the voltage domains. For example, the PMC may generate a high power domain reset signal for resetting the high power voltage domain, a low power domain reset signal for resetting the low power voltage domain, and an ultra-low power domain reset signal for resetting the ultra-low power voltage domain.
The voltage domains must be reset synchronously when the IC is powered up. If the voltage domains are not reset synchronously, the IC may enter a meta-stable state. Hence, the domain reset signals must be generated synchronously. However, due to varying propagation delays and on-chip variations, the domain reset signals may be skewed causing the voltage domains to be reset asynchronously, which can degrade the performance of the IC.
It would be advantageous to have a PMC that synchronously resets multiple voltage domains and prevents malfunctioning of the IC due to non-synchronous resetting of the voltage domains.